Advanced self-alignment process technique with very thick sidewall for high speed GaAs LSIs

Abstract

The authors describe the performance of 0.5- mu m-gate GaAs MESFETs with the two-step n/sup +/ structure, which consists of shallowly doped n/sup +/ and deeply doped n/sup ++/ regions. To realize such a structure, a very-thick-sidewall process was developed. The maximum transconductance was as high as 420 mS/mm, and the standard deviation of the threshold voltage was as low as 26.4 mV over a 3-in wafer. The minimum propagation delay time of a directly-coupled FET-logic inverter IC implemented with this technology was 11.0 ps/gate at a power dissipation of 25.2 mW/gate. A 1/8 static frequency divider operated at a frequency of up to 16 GHz, and a D-type flip-flop recorded at a data rate of 10 Gb/s. >