Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling

Abstract

A hierarchical two-dimensional field solution technique isintroduced for capacitance extraction for VLSI interconnectmodeling. As a basis for compromise between the efficiencyof Boolean rules-based extraction and the accuracy of flatfield solution, this hierarchical approach can handlerealistic conductor cross-sections and multiple conformaland/or planarized dielectrics.