IEEE Transactions on Computers · 1979 · 68 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsVlsi DesignConfigurable Logic BlocksDigital Logic DesignField-programmable Gate Array ArchitectureLogic SynthesisProgrammable Logic DevicesField-programmable Gate Arrays (Fpgas)Field-programmable Logic ArraysLogic Function ImplementationLogic OptimizationOn-chip InterconnectsProgrammable Logic ArrayProgrammable Logic Array DesignProgrammable Logic Design
A programmable logic array (PLA) chip design using special array folding techniques and an on-chip bus structure has been developed. It overcomes the sparseness in conventional large PLA configurations. The design is a masterslice FET chip personalized for the particular application during processing. Software algorithms are used to map conventional PLA formats into the new structure. The techniques used provide improved logic function and performance for an FET array technology. Included are descriptions of the PLA architecture and the circuitry that was used.
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An Introduction to Array Logic
H. Fleisher, L. I. Maissel · IBM Journal of Research and Development · 1975 · 188 citations