Challenges in hardening technologies using shallow-trench isolation

TLDR

Challenges related to radiation hardening CMOS technologies with shallow‑trench isolation are explored. The study investigates mechanisms that limit total‑dose radiation hardness in shallow‑trench isolated CMOS, such as high electric fields and ion‑implantation damage. Device simulations combined with test‑structure measurements are used to gain physical insight into improving total‑dose radiation response of shallow‑trench isolated CMOS. Developing radiation‑hardened shallow‑trench isolated CMOS is more complex than using field‑oxide isolation, yet the authors successfully converted Sandia's CMOS6 into a >1 Mrad(SiO₂) radiation‑hardened CMOS6r.

Abstract

Challenges related to radiation hardening CMOS technologies with shallow-trench isolation are explored. It is shown that developing a radiation-hardened CMOS technology with shallow trench isolation is more complex than using a traditional hardened field oxide as the trench insulator. We illustrate the use of device simulations in concert with measurements on test structures to provide detailed physical insight into methods for improving total-dose radiation response. Mechanisms that can limit the total-dose radiation hardness of shallow trench isolation such as high electric fields and ion implantation damage are explored. We demonstrate the successful conversion of a non-radiation hardened technology with LOCOS isolation (Sandia's CMOS6) into a greater than 1 Mrad(SiO/sub 2/) radiation-hardened shallow-trench isolated technology (Sandia's CMOS6r).