Vertical InGaAs/InP Tunnel FETs With Tunneling Normal to the Gate

Abstract

Vertical n-channel tunnel field-effect transistors (FETs) based on compound semiconductors, in a new geometry with tunneling normal to the gate, are demonstrated for the first time using an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As/n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ,=0.53- >;1 GaAs/p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> InP heterojunction. At 300 K, the TFETs show an on-current of ~20 μA/μm and a minimum subthreshold swing (SS) of 130 mV/dec using an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric (EOT ~3.4 nm). Postdeposition annealing of the gate dielectric improves SS, and device passivation using atomic layer deposition can effectively prevent degradation of drain current over time. The clear negative differential resistance (NDR) observed in the tunnel junction and the trend toward NDR in the TFETs confirm that the transport mechanism in these FETs is interband tunneling.