2004 · 74 citations · 15 references
EngineeringComputer EngineeringComputer ScienceMicroelectronicsDelay ModelingTiming AnalysisAsynchronous Pipeline ExecutionData PipeliningDelay-insensitive CircuitsHardware PipeliningPipeline ArchitecturePipeline DesignPipelined Digital CircuitsPipelining
This paper introduces two new high-speed quasi delay insensitive (QDI) asynchronous pipeline templates. These new high throughput templates support complex non-linear pipeline structures and are well suited for fine-grain pipelining. Timing analysis and HSPICE simulations show that these templates are 20% and 40% faster than known QDI counterparts.
15
Ivan E. Sutherland · Communications of the ACM · 1989 · 1K citations · Full text
The design of an asynchronous MIPS R3000 microprocessor
Alain J. Martin, Andrew Lines, Rajit Manohar et al. · 2002 · 325 citations
Ivan E. Sutherland, Scott Fairbanks · 2002 · 250 citations
Engineering, Computer Engineering, Electrical Engineering +17
Pipelined Asynchronous Circuits
Andrew Lines · 1998 · 215 citations · Full text