IEEE Electron Device Letters · 1991 · 14 citations · 6 references
EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesBipolar Junction TransistorsDelay ModelingDevice ModelingIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsPropagation DelayBase ResistanceCircuit Delay ModelingCurrent-mode LogicCutoff FrequencyHigh-speed Circuit DesignLogic Gate DelayLogic GatesPropagation Delay Modeling
The effects of base resistance, base transit time, and junction capacitances play a key role in the propagation delay of high-speed bipolar logic gates. A simple device figure of merit for transistors used in current mode logic (CML) circuits, based on minimum propagation delay, is developed. This delay is derived from the large-signal 3-dB cutoff frequency of the CML gate. Results are shown to be applicable for a wide range of device and circuit parameters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Analysis and Design of Analog Integrated Circuits
W.R. Betts · Electronics and Power · 1978 · 3.8K citations