A radiation-hardened 10 K-gate CMOS gate array

Abstract

A radiation-hardened 10013-gate complementary metal-oxide-semiconductor (CMOS) gate array with a 5-V supply voltage has been designed and fabricated utilizing Si-gate epi-CMOS technology with two-level metallization. The n-channel (NMOS) and p-channel (PMOS) gate lengths in basic cells are 2 mu m. A 100-krad(Si) total-dose radiation hardness has been realized by introducing a thin field oxide between the source and drain diffusion layers and a thick field oxide in NMOS transistors in both the basic cells and the I/O cells, as well as a buried p/sup +/ diffusion layer under a poly-Si layer at the p-well edge in the basic cells, without sacrificing speed and performance. The gate array can be used to realize various kinds of radiation-tolerant logic LSIs for space and nuclear plant applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>