K. Yamamoto

Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

Y. Hirano, Takuji Matsumoto, Satoshi Maeda et al. · 2002 · 24 citations

Electrical Engineering, Engineering, Vlsi Design +13

A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving −96.4-dBm Sensitivity and −27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets

Masahisa Tamura, Hideyuki Takano, Hironori Nakahara et al. · IEEE Journal of Solid-State Circuits · 2020 · 21 citations

Electrical Engineering, −27-Dbm Tolerance, Bluetooth Low Energy +14

70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications

Takeru Matsumoto, Shoji Maeda, Kosuke Ota et al. · 2002 · 15 citations

Ghz F/sub Max/, World Record Data, Electrical Engineering +12

A GaAs RF transceiver IC for 1.9 GHz digital mobile communication systems

K. Yamamoto, K. Maemura, Yasumi Ohta et al. · 2002 · 13 citations

Electrical Engineering, Negative Voltage Generator, Engineering +11

A high power and high efficiency GaAs BPLDD SAGFET with WSi/W double-layer gate for mobile communication systems

N. Kasai, Masaki Noda, K. Ito et al. · 2002 · 12 citations

Electrical Engineering, Engineering, Rf Semiconductor +13