IEEE Transactions on Circuits & Systems II Express Briefs · 2012 · 12 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyCurrent-voltage CharacteristicsLeakage Power ReductionMemory DevicesMemory Subsystem DesignLeakage Current ModelingLeakage Current ReductionLow-voltage Cmos DesignMemory Circuit DesignRandom Access Memory (Ram)Static Random-access Memory DesignUltra-low-power CmosUltra-low-voltage Circuit Design
A small bitline sensing margin is one of the most challenging design obstacles for reliable ultra-low-voltage static random access memory (SRAM) implementation. This paper presents design techniques for bitline sensing margin enhancement using decoupled SRAMs. The proposed bitline-boosting current scheme improves the bitline sensing margin at a given bitline configuration. The bitline sensing margin can be further augmented by equalizing bitline leakage. Simulation using a 40-nm CMOS process shows that the proposed techniques achieve larger bitline sensing margin, wider operating temperature and supply range, and a larger number of cells per bitline.
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