Publication | Closed Access
Design and reliability challenges in nanometer technologies
233
Citations
2
References
2004
Year
Unknown Venue
EngineeringVlsi DesignComputer ArchitectureNanoelectronicsCmos Technology ScalingElectronic PackagingInstrumentationElectrical EngineeringHardware ReliabilityNanotechnologyComputer EngineeringDevice ReliabilityMicroelectronicsMicrofabricationParameter VariationTechnology ScalingApplied PhysicsReliability ChallengesCircuit ReliabilityVariation ToleranceBeyond Cmos
CMOS technology scaling is causing the channel lengths to be sub-wavelength of light. Parameter variation, caused by sub-wavelength lithography, will pose a major challenge for design and reliability of future high performance microprocessors in nanometer technologies. In this paper, we present the impact of these variations on processor functionality, predictability and reliability. We propose design and CAD solutions for variation tolerance. We conclude this paper with soft error rate scaling trends and soft error tolerant circuits for reliability enhancement.
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