A current testing for CMOS static RAMs

Abstract

RAM testing has become a crucial problem because the testing time becomes much longer with the increase of its capacity. In this paper, the authors propose a current testing for CMOS static RAMs. Firstly, to see what influence a fault has on a power supply current, they analyze the behavior of a single memory cell when a fault occurs. It is found that almost all faults affect power supply current when a write operation is executed. Based on this analysis, secondly, the authors discuss a current testing scheme, where an address decoder structure is modified such that a write operation can be simultaneously executed on all the memory cells in a testing mode. In this current testing scheme, since the whole memory cell array could be treated as if it were a single memory cell, the length of the test sequences is not dependent on the size of memory cell array and must be very short. Hence, the authors believe their current testing method is a promising candidate for testing CMOS static RAMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>