IEEE Electron Device Letters · 2003 · 170 citations · 7 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsIii-v SemiconductorsMetal-oxide-semiconductor Field-effect TransistorsOxide SemiconductorsSemiconductor Device MaterialsSemiconductor InterfacesThermal Properties Of SemiconductorsGate Dielectric EngineeringGate Oxide InterfacesGate Oxide Thickness EffectsGate OxidesGermanium Device MaterialsTransconductance
In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.
7
Strained Si NMOSFETs for high performance CMOS technology
K. Rim, Steven J. Koester, M. Hargrove et al. · 2002 · 152 citations
Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs