Determination of Manufacturing Resurf Process Window for a Robust 700V Double Resurf LDMOS Transistor

Abstract

Resurf (reduced surface field) devices are enormously sensitive to the optimum integrated charge and/or the distribution of charge in the drift region for maintaining a robust breakdown voltage. Nevertheless this optimal charge-balance is often interrupted by the influence of charges in the overlying mold compound and passivation layers, resulting in breakdown voltage degradation under high-voltage, high-temperature stress. As a result, the resurf process window is further squeezed following the reliability stress to maintain the optimal charge balance, hence the target breakdown voltage of over 700 V. This paper presents the optimization of resurf charge for maintaining a robust breakdown voltage, and hence establishes the manufacturing process windows (process implant doses) based on the reliability data in order to minimize yield loss in production.