EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesEmbedded Memory BlocksLeakage Power ReductionLow-power Digital Circuit DesignMemory DevicesMemory Subsystem DesignPower ManagementLow-power Memory CircuitsMemory Circuit DesignMemory Power ManagementNon-volatile MemoryNon-volatile Memory DesignPower-efficient Memory DesignSignal-to-noise RatioSubthreshold Leakage Reduction
This paper describes low-voltage RAM designs for stand-alone and embedded memories in terms of signal-to-noise-ratio designs of RAM cells and subthreshold-current reduction.First, structures and areas of current DRAM and SRAM cells are discussed. Next, low-voltage peripheral circuits that have been proposed so far are reviewed with focus on subthreshold-current reduction, speed variation, on-chip voltage conversion, and testing.Finally, based on the above discussion, a perspective is given with emphasis on needs for high-speed simple non-volatile RAMs, new devices/circuits for reducing active-mode leakage currents, and memory-rich SOC architectures.
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Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
A. Keshavarzi, Shuo Ma, S. Narendra et al. · 2001 · 178 citations