Proceedings of ESSCIRC · 2007 · 60 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignConverter TopologiesDynamic Power ReductionLow-power Digital Circuit DesignPower ManagementLow-power Logic DesignLow-voltage Cmos DesignSub-threshold OperationSwitching DelaySwitching Delay AnalysisThreshold LogicThreshold VoltageThreshold Voltage Control
A new level converter (LC) is proposed for logic voltage shifting between sub threshold voltage to normal high voltage. By employing 2 PMOS diodes, the LC shows good operation robustness with sub-threshold logic input. The switching delay of the proposed LC can adapt with the input logic voltage which is more suitable for power aware systems. With a simpler circuit structure, the energy consumption of the LC is smaller than that of the existing sub threshold LC. Simulation results demonstrate the performance improvement and energy reduction of the proposed LC. Test chip was fabricated using 0.18μm CMOS process. Measurement results show that our proposed LC can operate correctly with an input at as low as 127mV and an output voltage at 1.8V.
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