Switching Delay Analysis

Switching Delay Analysis is a formal methodological framework within the domain of circuit-switched networks that quantifies and evaluates the time latency incurred during the establishment, maintenance, and teardown phases of dedicated physical circuit connections, distinguishing it from packet-level delay analyses by focusing exclusively on circuit provisioning overhead.

179

Publications

6.5K

Citations

511

Authors

185

Institutions

Publications per year

2017–2026

15

Authors

511

  1. RE
    Rolf Ernst

    Technische Universität Braunschweig, Germany

    4 publications · 131 citations

    4

    h-index

  2. DS
    Devavrat Shah

    Massachusetts Institute of Technology, United States

    3 publications · 149 citations

    3

    h-index

  3. HT
    Hussein T. Mouftah

    University of Ottawa, Canada

    3 publications · 34 citations

    3

    h-index

  4. HY
    Hak Yong Kim

    Jeonbuk National University, South Korea

    2 publications · 34 citations

    2

    h-index

  5. CT
    Chi-Ying Tsui

    Hong Kong University of Science and Technology, Hong Kong SAR China

    2 publications · 83 citations

    2

    h-index

1–5 of 511

Venues

  1. IEEE Transactions on Electron Devices

    8 publications · 367 citations

    8

    h-index

  2. IEEE Journal of Solid-State Circuits

    6 publications · 143 citations

    6

    h-index

  3. Performance Evaluation

    5 publications · 82 citations

    5

    h-index

  4. IRE Transactions on Communications Systems

    5 publications · 139 citations

    5

    h-index

  5. IEEE Transactions on Computers

    5 publications · 227 citations

    5

    h-index

1–5