Switching Delay Analysis
Switching Delay Analysis is a formal methodological framework within the domain of circuit-switched networks that quantifies and evaluates the time latency incurred during the establishment, maintenance, and teardown phases of dedicated physical circuit connections, distinguishing it from packet-level delay analyses by focusing exclusively on circuit provisioning overhead.
179
Publications
6.5K
Citations
511
Authors
185
Institutions
Publications per year
2017–2026
15
Parents
179
The effective drive current in CMOS inverters
Mulun Na, E. Nowak, Wilfried Haensch et al. · 2003 · 238 citations
Engineering, Computer Engineering, Electrical Engineering +17
Joint On-Demand Routing and Spectrum Assignment in Cognitive Radio Networks
Ge Cheng, Wei Liu, Ya-Ping Li et al. · 2007 · 233 citations
Measuring control plane latency in SDN-enabled switches
Keqiang He, Junaid Khalid, Aaron Gember-Jacobson et al. · 2015 · 138 citations
1–5 of 179
511
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Hong Kong University of Science and Technology, Hong Kong SAR China
2 publications · 83 citations
2
h-index
1–5 of 511
185
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
8 h-index
28 publications
1.4K citations
University of Illinois Urbana-Champaign
Urbana, United States
6 h-index
12 publications
306 citations
IBM (United States)
Armonk, United States
6 h-index
22 publications
1.5K citations
Stanford University
Stanford, United States
5 h-index
8 publications
166 citations

Huazhong University of Science and Technology
Wuhan, China
4 h-index
17 publications
1.2K citations
Massachusetts Institute of Technology
Cambridge, United States
4 h-index
8 publications
390 citations
Georgia Institute of Technology
Atlanta, United States
3 h-index
12 publications
498 citations

University of Victoria
Victoria, Canada
3 h-index
7 publications
139 citations
1–8 of 185
8 publications · 367 citations
8
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6 publications · 143 citations
6
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5 publications · 82 citations
5
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5 publications · 139 citations
5
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5 publications · 227 citations
5
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