Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> DC and high-frequency device characteristics of <formula formulatype="inline"><tex Notation="TeX">$\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$</tex></formula> and InSb quantum-well field-effect transistors (QWFETs) are measured and benchmarked against state-of-the-art strained silicon (Si) nMOSFET devices, all measured on the same test bench. Saturation current <formula formulatype="inline"><tex Notation="TeX">$(I_{\rm on})$</tex></formula> gain of 20% is observed in the <formula formulatype="inline"><tex Notation="TeX">$\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$</tex></formula> QWFET over the strained Si nMOSFET at <formula formulatype="inline"><tex Notation="TeX">$(V_{g} - V_{t}) = \hbox{0.3}\ \hbox{V}$</tex></formula>, <formula formulatype="inline"><tex Notation="TeX">$V_{\rm ds} = \hbox{0.5}\ \hbox{V}$</tex></formula>, and matched <formula formulatype="inline"><tex Notation="TeX">$I_{\rm off}$</tex></formula>, despite higher external resistance and large gate-to-channel thickness. To understand the gain in <formula formulatype="inline"><tex Notation="TeX">$I_{\rm on}$</tex></formula> , the effective carrier velocities <formula formulatype="inline"><tex Notation="TeX">$(\nu_{\rm eff})$</tex></formula> near the source-end are extracted and it is observed that at constant <formula formulatype="inline"><tex Notation="TeX">$(V_{g} - V_{t}) = \hbox{0.3}\ \hbox{V}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$V_{\rm ds} = \hbox{0.5}\ \hbox{V}$ </tex></formula>, the <formula formulatype="inline"><tex Notation="TeX">$\nu_{\rm eff}$</tex></formula> of <formula formulatype="inline"><tex Notation="TeX">$\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$</tex></formula> and InSb QWFETs are 4–5<formula formulatype="inline"><tex Notation="TeX">$\times$</tex></formula> higher than that of strained silicon (Si) nMOSFETs due to the lower effective carrier mass in the QWFETs. The product of <formula formulatype="inline"><tex Notation="TeX">$ \nu_{\rm eff}$</tex></formula> and charge density <formula formulatype="inline"><tex Notation="TeX">$(n_{s})$</tex></formula>, which is a measure of “intrinsic” device characteristics, for the QWFETs is 50%–70% higher than strained Si at low-voltage operation despite lower <formula formulatype="inline"><tex Notation="TeX">$n_{s}$</tex></formula> in QWFETs. Calibrated simulations of <formula formulatype="inline"><tex Notation="TeX">$\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$</tex> </formula> QWFETs with reduced gate-to-channel thickness and external resistance matched to the strained Si nMOSFET suggest that the higher <formula formulatype="inline"><tex Notation="TeX">$\nu_{\rm eff}$</tex></formula> will result in more than 80% <formula formulatype="inline"><tex Notation="TeX">$I_{\rm on}$</tex></formula> increase over strained Si nMOSFETs at <formula formulatype="inline"><tex Notation="TeX">$V_{\rm ds} = \hbox{0.5}\ \hbox{V}$</tex></formula>, <formula formulatype="inline"><tex Notation="TeX">$(V_{g} - V_{t}) = \hbox{0.3}\ \hbox{V}$</tex></formula>, and matched <formula formulatype="inline"><tex Notation="TeX">$I_{\rm off}$</tex></formula>, thus showing promise for future high-speed and low-power logic applications. </para>