Implementation of buffered Super-Junction LDMOS in a 0.18um BCD process

Abstract

We experimentally demonstrate a super-junction LDMOS transistor in a 0.18 mum BCD technology. The buffered super-junction structure is implemented by the use of existing N- and P-drift layer, which are optimized for conventional 20 V to 30 V LDMOS transistors. The breakdown voltage and the specific on-resistance of the fabricated super-junction LDMOS are 98.6 V and 1.01 mOmegaldrcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. The TLP measurement results show fairly good electrical SOA characteristics up to 78 V for all gate voltages.