Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

Abstract

This work demonstrates that the 2× mobility advantage of (110) PMOS over (100) PMOS is maintained down to 190nm poly-pitch for devices under compressive stress. (110) PMOS with 3.5GPa compressively stressed liners demonstrate strong channel drives with I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> =800 μA/μm at I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> =100nA/μm (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> =1.0V) for 190nm poly-pitch, the highest reported to date for 45-nm-node (110) PMOS using conventional gate dielectrics without eSiGe stressors. Additionally, (110) PMOS show better scalability, with 15% smaller total I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> degradation than (100) PMOS when poly-pitch scales from 250nm to 190nm.