IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1997 · 43 citations · 27 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignNoise In Electronic DevicesNoise In Semiconductor DevicesTiming AnalysisCmos Inverter DesignComplementary Metal-oxide-semiconductor Inverter DesignInvertersParasitic Inductance EffectsSaturation EffectsSignal Propagation DelaySimultaneous Switching NoiseVelocity Saturation
Complementary metal‑oxide‑semiconductor output buffers of tapered inverters drive large off‑chip capacitances, with the taper factor defined by the transistor size ratio between stages, and high‑frequency simultaneous switching causes parasitic inductance at the pin‑pad‑package interface to generate significant switching noise on the power lines. The study presents a comprehensive analysis and estimate of simultaneous switching noise (SSN) in output drivers. The analysis includes velocity saturation effects in submicron transistors during driver switching. SSN increases buffer propagation delay and transition time, raises the optimum taper factor for a given load, and beyond a critical value causes transition time to rise as taper factor decreases, while skewing buffer switching with additional inverter stages can reduce SSN at the cost of longer propagation delay.
Complementary metal-oxide-semiconductor (CMOS) output buffers, comprised of a series of tapered inverters, are used to drive large off-chip capacitances. The ratio of the size of transistors between two consecutive stages is the buffer taper factor. With higher frequency of operation and simultaneous switching of the output drivers, the parasitic inductance present at the pin-pad-package interface results in significant switching noise on the power lines. A comprehensive analysis and estimate of simultaneous switching noise (SSN) including the velocity saturation effects seen in the submicron transistors during the switching of output drivers is presented. The effect of SSN on the overall buffer propagation delay and transition time is discussed. The presence of SSN results in an increase in the optimum taper factor between inverter stages for a given capacitive load. Beyond a critical value, the output transition time of a tapered buffer increases with reducing taper factor due to SSN. SSN can be reduced by skewing the switching of output buffers, SPICE simulation results show that skewing buffer switching with additional inverter stages reduces SSN and increases buffer propagation delay.
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