IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1993 · 21 citations · 8 references
EngineeringComputer EngineeringComputer ScienceAlgorithmsDesign OptimizationOptimizationBranch And BoundLayout OptimizationLogic SynthesisPhysical DesignVery-large-scale Integration LayoutArea OptimizationBasic Block AnalysisBlock Size DeterminationFloorplanningIntegrated Circuit FloorplanningPlacement AlgorithmsSlicingVlsi Implementation
The problem of selecting a realization for each of the blocks in a VLSI chip's floorplan so that the area of the floorplan is minimized is considered. This is done by repeatedly replacing primitive superblocks by equivalent basic blocks. A linear time algorithm to determine all the needed primitive superblocks is developed. Equivalent basic blocks are found by using L. Stockmeyer's (1983) algorithm if the primitive superblock has a slicing structure and by using branch-and-bound if not. Experimental results are provided.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
8