IEEE Journal of Solid-State Circuits · 1990 · 65 citations · 6 references
Low-power ElectronicsElectrical EngineeringEngineeringCircuit SystemPower CircuitPower Optimization (Eda)Digital Cmos CircuitsVoltage ReductionPower Electronics ConverterComputer EngineeringElectric Power ConversionDigital Circuit DesignPower ElectronicsVoltage Reduction TechniquePower ConsumptionPower-aware Design
Two techniques for voltage reduction are presented, both of which can significantly reduce the power consumption of digital CMOS circuits. The fixed reduction of voltage is applicable to small systems with a low initial consumption, however, the optimum voltage is not reached and the correct operation of the circuit is not guaranteed. The self-adjusted reduction of voltage is adapted to bigger digital systems. The correct operation of the digital circuit is guaranteed, and the supply voltage is near the optimum for the speed requirements. This technique is more versatile, accurate, and reliable than the fixed one.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
6
Adaptive biasing CMOS amplifiers
M. Degrauwe, J. Rijmenants, Eric A. Vittoz et al. · IEEE Journal of Solid-State Circuits · 1982 · 280 citations
Low-power Electronics, Electrical Engineering, Engineering +10
An experimental 1Mb DRAM with on-chip voltage limiter
Circuit techniques for a VLSI memory
T. Mano, J. Yamada, Junpei Inoue et al. · IEEE Journal of Solid-State Circuits · 1983 · 33 citations
Hardware Security, Threshold Imbalance, Electrical Engineering +11