IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987 · 53 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSimulation-based DesignDesign For TestabilityDesign SimulationDevice ModelingDevice SimulationElectric CircuitsTiming AnalysisCircuit Delay ModelingCircuit SimulationCompact ModelingElectric Circuit ModelsGlitch AnalysisSwitch SimulationSwitching Activity AnalysisTiming
This paper addresses various timing and glitch detection issues in switch-level simulation. Particular attention is focused on charge sharing. We categorize and analyze problems caused by charge sharing. Solutions to these problems are proposed and applied to real designs. Results are reported and compared with SPICE simulation. The computational complexity of our methods is also investigated.
13
Timing Models for MOS Circuits
Mark Horowitz · 1983 · 199 citations
Engineering, Computer Engineering, Electrical Engineering +16
Signal Delay in RC Tree Networks
P. Penfield, J. Rubinstein · 18th Design Automation Conference · 1981 · 142 citations