IEEE Journal of Solid-State Circuits · 2000 · 11 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringMemoryMicroelectronicsSemiconductor DevicesDevice ReliabilityEmbedded Memory BlocksLeakage Power ReductionMemory DevicesThermal ManagementArray DesignData RetentionFowler-nordheim TunnelingLeakageMemory Array ArchitectureMemory Circuit DesignNon-volatile Memory DesignTunneling Effects
A 1-Kbit high-temperature EEPROM memory module has been developed in a 1.6-/spl mu/m thin-film SIMOX technology. The memory array is based on single-poly EEPROM cells, which are erased and programmed by Fowler-Nordheim tunneling. Operation at elevated temperatures is achieved by a special array design, suitable for elimination of cell-disturb problems caused by temperature-induced leakage currents of the select transistors. High-voltage switching is done without PMOS transistors in order to avoid leakage currents due to the backgate effect. The memory module is designed for 5-V only operation and offers an access time of 260 ns at an operating temperature of 250/spl deg/C. At 250/spl deg/C, data retention of 3000 h and an endurance of 10000 erase/program cycles has been achieved. The area of the 1-Kbit memory module is 0.89/spl times/2.71 mm/sup 2/.
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A 5V-only 16K EEPROM utilizing oxynitride dielectrics and EPROM redundancy
Akhil Gupta, Te-Long Chiu, Maria Chang et al. · 1982 · 25 citations
Engineering, Computer Engineering, Electrical Engineering +17
An 80 ns 32K EEPROM using the FETMOS cell
C. Kuo, J.R. Yeargain, William Downey et al. · IEEE Journal of Solid-State Circuits · 1982 · 17 citations
Engineering, Computer Engineering, Electrical Engineering +13