Electronics Letters · 1999 · 38 citations · 1 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSemiconductor MaterialsDevice ModelingDevice SimulationIntegrated Circuit DevicesMetal-oxide-semiconductor Field-effect TransistorsSemiconductor Thin FilmsThin-film TransistorsFully Depleted Silicon-on-insulator ScalingFully Depleted Silicon-on-insulator TransistorsGround Plane EffectsNumerical Device SimulationNumerical SimulationSilicon-on-insulator CmosSilicon-on-insulator TechnologySubthreshold Slope Engineering
A method for fabricating a back-gate ground plane underneath a thin-film silicon-on-insulator (SOI) MOSFET is described. It is shown by numerical simulation that the formation of the ground plane improves the subthreshold slope and short-channel characteristics of very short-channel devices.
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