IEEE Transactions on Nuclear Science · 1997 · 80 citations · 12 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSemiconductor MaterialsCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ScalingDevice SimulationIntegrated Circuit DesignMemory DevicesComplementary Metal-oxide-semiconductor SimulationDevice Scaling EffectsDynamic Random-access Memory DesignMemory Circuit DesignMemory Device SimulationScaling Effects In CmosStatic Random-access Memory DesignSubthreshold Conduction
This work presents SEU phenomena in advanced SRAM memory cells. Using mixed-mode simulation, the effects of scaling on the notions of sensitive area and critical charge is shown. Specifically, we quantify the influence of parasitic bipolar action in cells fabricated in a submicron technology.
12
Single event upset at ground level
E. Normand · IEEE Transactions on Nuclear Science · 1996 · 611 citations
Impact of technology trends on SEU in CMOS SRAMs
P.E. Dodd, F.W. Sexton, G.L. Hash et al. · IEEE Transactions on Nuclear Science · 1996 · 126 citations
Engineering, Computer Engineering, Electrical Engineering +17