Design of a Stable Read-Decoupled 6T SRAM Cell at 16-Nm Technology Node

Abstract

This work presents a new single-port 6T SRAM cell with a single-ended read operation (read-decoupled) and shows significant improvement in read stability and write-ability as compared to the conventional 6T (CON6T) SRAM cell. Unlike the CON6T cell where the pull-up transistors are powered by the supply voltage (VDD), the proposed cell has powered these transistors by the bit line driver. Another distinct feature of the proposed design is the presence of a PMOS transistor between the two storage nodes which is used during the write operation. The design metrics of proposed stable read-decoupled 6T SRAM cell are compared with those of the CON6T SRAM cell. The proposed cell shows 4× improvement in read static noise margin (RSNM) and 8% improvement in write static noise margin (WSNM) @ 700 mV.