A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS

Abstract

Low-power portable electronics such as implantable medical devices require low-access-energy non-volatile memory to deliver longer battery lifetime and richer functionality. Ferroelectric random access memory (FeRAM) technology is a good candidate for both storage and non-volatile RAM. The power and supply voltage of FeRAM need further reduction, and this work presents a solution in anticipation of FeRAM scaling to advanced technology nodes for which the bitcell charge reduces and transistors operate at 1V and below. Specifically, a time-to-digital converter (TDC) sensing scheme is developed to capture the diminishing charge signal from the memory element at low supply voltage.