The channeled-BSG

Abstract

Article The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications Share on Authors: Shigetoshi Nakatake Department of Electrical and Electronic Engineering, Tokyo Institute of Technology Department of Electrical and Electronic Engineering, Tokyo Institute of TechnologyView Profile , Keishi Sakanushi Department of Electrical and Electronic Engineering, Tokyo Institute of Technology Department of Electrical and Electronic Engineering, Tokyo Institute of TechnologyView Profile , Yoji Kajitani Department of Electrical and Electronic Engineering, Tokyo Institute of Technology Department of Electrical and Electronic Engineering, Tokyo Institute of TechnologyView Profile , Masahiro Kawakita Semiconductor Systems Engineering Center, Toshiba Corporation Semiconductor Systems Engineering Center, Toshiba CorporationView Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 418–425https://doi.org/10.1145/288548.289064Online:01 November 1998Publication History 9citation195DownloadsMetricsTotal Citations9Total Downloads195Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access