Floorplanning For Network-on-chip

Floorplanning for Network-On-Chip is a design methodology within integrated circuit physical synthesis that specifically determines the optimal placement and spatial organization of intellectual property cores and network infrastructure elements to minimize communication latency, area overhead, and power consumption while adhering to performance and routing constraints in a chip-scale network architecture.

Publications

Citations

191

Authors

Institutions

Publications per year

2017–2026

Parents

Network-on-chip Design

Publications

Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation

Brett Feero, Partha Pratim Pande · IEEE Transactions on Computers · 2008 · 463 citations

Engineering, Computer Engineering, Electrical Engineering +17

SUNMAP

Srinivasan Murali, Giovanni De Micheli · 2004 · 325 citations

Engineering, Computer Engineering, Computer Science +17

Designing application-specific networks on chips with floorplan information

Srinivasan Murali, Paolo Meloni, Federico Angiolini et al. · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2006 · 205 citations · Full text

Engineering, Computer Engineering, Computer Science +17

Network-on-Chip design and synthesis outlook

David Atienza, Federico Angiolini, Srinivasan Murali et al. · Integration · 2008 · 125 citations · Full text

Engineering, Computer Engineering, Computer Science +14

A design methodology for application-specific networks-on-chip

Jiang Xu, Wayne Wolf, Joerg Henkel et al. · ACM Transactions on Embedded Computing Systems · 2006 · 100 citations

Engineering, Computer Engineering, Computer Science +17

1–5 of 73

Authors

191

SC
Song Chen
University of Science and Technology of China, China
8 publications · 149 citations
8
h-index
SG
Satoshi Goto
Waseda University, Japan
5 publications · 108 citations
5
h-index
SM
Srinivasan Murali
École Polytechnique Fédérale de Lausanne, Switzerland
5 publications · 735 citations
5
h-index
LB
Luca Benini
University of Bologna, Italy
5 publications · 468 citations
5
h-index
GD
Giovanni De Micheli
École Polytechnique Fédérale de Lausanne, Switzerland
5 publications · 735 citations
5
h-index

1–5 of 191

Institutions

1–8 of 77

Venues

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
8 publications · 310 citations
8
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
5 publications · 194 citations
5
h-index
Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design
ICCAD · 2 publications · 244 citations
2
h-index
ACM Transactions on Design Automation of Electronic Systems
TODAES · 2 publications · 25 citations
2
h-index
IEEE Transactions on Computers
2 publications · 497 citations
2
h-index

1–5