A design methodology for application-specific networks-on-chip

TLDR

System‑on‑chip designs increasingly rely on hardware/software codesign to lower cost and improve reliability, yet the growing complexity of on‑chip communication subsystems has outpaced existing design methodologies. This work introduces an application‑specific networks‑on‑chip (ASNoC) concept and a design methodology to generate optimized ASNoCs for specific SoC applications. The methodology automatically generates an ASNoC and its distributed shared memory from recorded or statistical communication traces, leveraging a standardized component library and the OPNET simulation environment to estimate power, area, and performance, and is demonstrated on H.264 HDTV decoder and smart camera SoCs. Compared with 2D mesh networks, the ASNoC delivers significant gains, achieving up to 2× performance while reducing power by 39 %, silicon area by 59 %, metal area by 74 %, switch capacity by 63 %, and interconnection capacity by 69 % in the H.264 HDTV decoder SoC.

Abstract

With the help of HW/SW codesign, system-on-chip (SoC) can effectively reduce cost, improve reliability, and produce versatile products. The growing complexity of SoC designs makes on-chip communication subsystem design as important as computation subsystem design. While a number of codesign methodologies have been proposed for on-chip computation subsystems, many works are needed for on-chip communication subsystems. This paper proposes application-specific networks-on-chip (ASNoC) and its design methodology. ASNoC is used for two high-performance SoC applications. The methodology (1) can automatically generate optimized ASNoC for different applications, (2) can generate a corresponding distributed shared memory along with an ASNoC, (3) can use both recorded and statistical communication traces for cycle-accurate performance analysis, (4) is based on standardized network component library and floorplan to estimate power and area, (5) adapts an industrial-grade network modeling and simulation environment, OPNET, which makes the methodology ready to use, and (6) can be easily integrated into current HW/SW codesign flow. Using the methodology, ASNoC is generated for a H.264 HDTV decoder SoC and Smart Camera SoC. ASNoC and 2D mesh networks-on-chip are compared in performance, power, and area in detail. The comparison results show that ASNoC provide substantial improvements in power, performance, and cost compared to 2D mesh networks-on-chip. In the H.264 HDTV decoder SoC, ASNoC uses 39% less power, 59% less silicon area, 74% less metal area, 63% less switch capacity, and 69% less interconnection capacity to achieve 2X performance compared to 2D mesh networks-on-chip.