Optimization of V/sub DD/ and V/sub TH/ for low-power and high-speed applications

Abstract

Closed-form formulas are presented for optimum supply voltage (V/sub DD/) and threshold voltage (V/sub TH/) that minimize power dissipation when technology parameters and required speed are given. The formulas take into account short-channel effects and the variation of V/sub TH/ and temperature. Using typical device parameters, it is shown that a simple guideline to optimize the power consumption is to set the ratio of maximum leakage power to total power about 30%. Extending the analysis, the future VLSI design trend is discussed. The optimum V/sub DD/ coincides with the SIA roadmap and the optimum V/sub TH/ for logic blocks at the highest temperature and at the lowest process variation corner is in the range of 0 V-0.1 V over generations.