2002 · 131 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesBuilt-in Self-testCmos Circuit DesignDevice CharacterizationLow-power Digital Circuit DesignCmos ScalingLow-power Cmos DesignLow-power Design For TestabilityLow-voltage Cmos DesignPower-delay ProductPower-delay TradeoffThreshold VoltageThreshold Voltage Scaling
A CMOS test chip that includes a 1k-transistor self-testing encoder/decoder is verifiably error-free at supply voltages down to 20O mV, achieving 1/625 the power-delay product of standard 5 V CMOS. The maximum error-free operating frequency of this circuit as a function of supply and threshold voltage is reported here and voltage scaling of performance is compared with ring-oscillator data reported earlier. The circuit works even when bodies of transistors are forward-biased relative to sources to induce /spl sim/100mV depletion-mode thresholds.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>