On the assessment of voids in the thermal interface material on the thermal performance of a silicon chip package

The effect of die attach voiding on the thermal resistance of chip level packages

Amy S. Fleischer, Li-Hsin Chang, Barry C. Johnson · Microelectronics Reliability · 2005 · 102 citations

Engineering, Materials Engineering, Materials Science +14

Challenges in Cooling Design of CPU Packages for High-Performance Servers

Jie Wei · Heat Transfer Engineering · 2008 · 100 citations

Engineering, Computer Engineering, Materials Engineering +17

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Kenny C. Otiaba, Raj Bhatti, N.N. Ekere et al. · Microelectronics Reliability · 2012 · 64 citations

Engineering, Computer Engineering, Electrical Engineering +17

Modelling thermal effects of large contiguous voids in solder joints

L. Ciampolini, Mauro Ciappa, P. Malberti et al. · Microelectronics Journal · 1999 · 49 citations

Engineering, Electrical Engineering, Materials Engineering +17

Voids in thermal interface material layers and their effect on thermal performance

A. Gowda, David Esler, Sandeep Tonapi et al. · 2005 · 42 citations

Engineering, Materials Engineering, Materials Science +17