International Journal of Reconfigurable Computing · 2011 · 17 citations · 14 references
EngineeringHardware Verification LanguageComputer ArchitectureSoftware EngineeringSensitive User ModuleEmbedded SystemsHardware SystemsSoftware AnalysisFormal VerificationHardware Verification LanguagesHardware SecurityReliability EngineeringFault Injection AnalysisLinux OperatingHardware VerificationFpga-based Linux Test-bedComputer EngineeringFpga-embedded PlatformComputer ScienceDesign For TestingEmbedded Operating SystemHardware EmulationOperating SystemsProgram AnalysisSoftware TestingFault AttackFault InjectionSystem SoftwareLinux Os
An FPGA-based Linux test-bed was constructed for the purpose of measuring its sensitivity to single-event upsets. The test-bed consists of two ML410 Xilinx development boards connected using a 124-pin custom connector board. The Design Under Test (DUT) consists of the “hard core” PowerPC, running the Linux OS and several peripherals implemented in “soft” (programmable) logic. Faults were injected via the Internal Configuration Access Port (ICAP). The experiments performed here demonstrate that the Linux-based system was sensitive to 199,584 or about 1.4 percent of all tested bits. Each sensitive bit in the bit-stream is mapped to the resource and user-module to which it configures. A density metric for comparing the reliability of modules within the system is presented. Using this density metric, we found that the most sensitive user module in the design was the PowerPC's direct connections to the DDR2 memory controller.
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A fault injection analysis of Virtex FPGA TMR design methodology
F. Lima, C. Carmichael, J. Fabula et al. · 2005 · 129 citations