Bell System Technical Journal · 1978 · 62 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryFault-tolerant SystemsMicroelectronicsCmos Circuit DesignDesign For TestabilityDigital Integrated Circuit DesignDigital Integrated CircuitsFault DetectionFault DiagnosisDiagnostic Test GenerationDigital Circuit Self-testingFault CoverageFault Coverage AnalysisFault Coverage ModelingFault SimulationHardware Fault ModelsStuck-at Fault Testing
A theoretical expression is derived in this paper that evaluates the effectiveness of a set of logic tests for digital integrated circuits. The validity of the proposed figure of merit is examined with experimental data from CMOS integrated circuits. In addition, the importance of simulating the nonclassical stuck-open/stuck-on CMOS logic faults is also studied.
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Probability Plotting Methods for the Analysis of Data
M. B. Wilk, R. Gnanadesikan · Biometrika · 1968 · 1.2K citations
<i>LAMP</i>: System Description
H. Y. Chang, G. Smith, R. B. Walford · Bell System Technical Journal · 1974 · 73 citations
Engineering, Electrical Engineering, Systems Engineering +17
Diagnostics for logic networks
Alfred K. Susskind · IEEE Spectrum · 1973 · 19 citations