An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes

Abstract

Digital near-threshold logic circuits have recently been proposed for applications in the ultra-low power end of the design spectrum, where the performance is of secondary importance. However, the characteristics of MOS transistors operating in the near-threshold region are very different from those in the strong-inversion region. This paper first derives the logical effort and parasitic delay values for logic gates in multiple voltage (sub/near/super-threshold) regimes based on the transregional model. The transregional model shows higher accuracy for both sub- and near-threshold regions compared with the subthreshold model. Furthermore, the derived near-threshold logical effort method is subsequently used for delay optimization of circuits operating in both near- and super-threshold regimes. In order to achieve this goal, a joint optimization of transistor sizing and adaptive body biasing is proposed and optimally solved using geometric programming. Experimental results show that our improved logical effort-based optimization framework provides a performance improvement of up to 40.1% over the conventional logical effort method.