Experimental technology and performance of 0.1-µm-gate-length FETs operated at liquid-nitrogen temperature

Abstract

An overview is presented of our work to explore the extendibility of the silicon FET technology to the 0.1-µm-gate-length level. Self-aligned, n-channel, polysilicon-gated FETs were designed for operation at 77K, with reduced power-supply voltage. Direct-write electron-beam lithography was used to pattern all levels, while other processing followed established lines. Noteworthy results of the work included the observation of a clear manifestation of velocity overshoot, which contributed to achieving extrinsic transconductances above 940 µS/µm at 0.07-µm gate length. The measured switching delay of ring oscillators which contained 0.1-µm-gate-length devices was as low as 13.1 ps, with simulations showing potential for reduction to below 5 ps. Both the transconductance and the switching times are the best values observed for FETs to date-indicating continuing value in the scaling of FETs to dimensions well beyond those currently used.