Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2011 · 17 citations · 0 references
EngineeringComputer EngineeringComputer ScienceComputer-aided DesignDesign AutomationDigital FabricationDigital Integrated Circuit DesignDigital Logic DesignIntegrated Circuit DesignPhysical DesignStandard Cell DesignVery-large-scale Integration LayoutDouble Patterning LayoutLogic Block DesignLogic Block Placement StrategiesLogic Family DesignLogic Gate ImplementationSelf-aligned PatterningSpacer TechnologyStandard Cell Placement
Double patterning technology (DPT) is the only solution to enable the scaling for advanced technology nodes before EUV or any other advanced patterning techniques become available. In general, there are two major double patterning techniques: one is Litho-Etch-Litho-Etch (LELE), and the other is sidewall spacer technology, a Self-Aligned Double Patterning technique (SADP). While numerous papers have previously demonstrated these techniques on wafer process capabilities and processing costs, more study needs to be done in the context of standard cell design flow to enable their applications in mass production. In this paper, we will present the impact of DPT on logic designs, and give a thorough discussion on how to make DPT-compliant constructs, placement and routing using examples with Cadence's Encounter Digital Implementation System (EDI System).