2012 · 46 citations · 5 references
EngineeringComputer EngineeringComputer ScienceFault ToleranceMicroelectronicsSemiconductor DevicesMemory DevicesMemory Subsystem DesignSolid-state Storage3D Nand ArchitectureFlash MemoryFlash Memory DevicesHigh PerformanceNand Flash MemoryNand Flash Memory OrganizationNon-volatile Memory DesignThroughput
Since the first 3b/cell (X3) NAND flash memory paper in ISSCC 2008 [1], market demand for applications using high-density low-cost flash memory such as tablets, smart phones, and SSDs, has increased rapidly. Various electronic devices already use X3 NAND. The use of all BL (ABL) architecture, advanced circuitry, and enhanced algorithms enables this work to achieve 18MB/s performance, allowing penetration of markets where 2b/cell (D2) NAND has been used. As NAND memory scales aggressively towards 10nm, achieving the same level of performance with X3 chips is increasingly difficult. This paper addresses challenges with improvements made over previous NAND generations to achieve high performance while maintaining a low fail-bit count (FBC) and cost savings from an improved architecture and tightly packed peripheral circuits. Air gap [2,3] technology further improves write throughput by reducing neighbor interference and WL RC. A toggle mode 400Mb/s I/O interface reduces system overhead and enhances overall performance.
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A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS
Cuong Trinh, Noboru Shibata, Takumi Nakano et al. · 2009 · 69 citations
Engineering, Computer Engineering, Electrical Engineering +16
G. Marotta, A. Macerola, Antonino D’Alessandro et al. · 2010 · 53 citations
A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate
Yan Li, Seungpil Lee, Yupin Fong et al. · 2008 · 47 citations · Full text