Strained tunnel FETs with record I<inf>ON</inf>: first demonstration of ETSOI TFETs with SiGe channel and RSD

Abstract

We present for the first time Tunnel FETs obtained with a FDSOI CMOS process flow featuring High-K Metal Gate, ultrathin body compressively strained Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> (x from 0 to 30%) based channels, and Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> Raised SD. We analyse the tunnelling improvements due to the different technological injection boosters: ultrathin body & EOT, strain, low band gap source, and low temperature SD anneal. For the first time, TFETs with large ON current (up to 428μA/μm) are demonstrated (with >;x1000 I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> gain vs. SOI).