Concepedia

Delay-testable implementations of symmetric functions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1995 · 19 citations · 5 references

Concepts

EngineeringComputer EngineeringComputer ScienceTheory Of ComputationBoolean AlgebraDesign For TestabilityTiming AnalysisBoolean Circuit EvaluationBoolean Function DecompositionDelay-insensitive CircuitsMinimization Of Boolean FunctionsMulti-level ImplementationSymmetric Function TheorySymmetric Functions

Abstract

We show that most symmetric functions do not have delay-testable two-level implementations. A method of transforming any untestable minimal two-level implementation of a symmetric function into a delay-testable three- or four-level one using the distributive law is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

References

5

On Delay Fault Testing in Logic Circuits

Chin Jen Lin, S.M. Reddy · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987 · 562 citations

Engineering, Computer Engineering, Electrical Engineering +16

On the design of path delay fault testable combinational circuits

A.K. Pramanick, S.M. Reddy · 2002 · 105 citations

Engineering, Computer Engineering, Electrical Engineering +9

Synthesis of robust delay-fault-testable circuits: theory

Srinivas Devadas, Kurt Keutzer · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1992 · 98 citations

Engineering, Computer Engineering, Electrical Engineering +12

Synthesis of multi-level combinational circuits for complete robust path delay fault testability

N.H. Jha, Irith Pomeranz, S.M. Reddy et al. · 2003 · 31 citations

Engineering, Computer Engineering, Computer Science +17

Generating minimal covers of symmetric functions

D.L. Dietmeyer · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1993 · 22 citations

Computing, Computer Engineering, Computer Science +11