Realizing super-steep subthreshold slope with conventional FDSOI CMOS at low-bias voltages

Abstract

We report the first demonstration of a super-steep subthreshold slope (SS) (the smallest ever reported experimentally) with ultra-thin BOX (UTBOX) FDSOI standard CMOS transistors. Record steep SS of 72μV/dec for L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> =25nm and 58μV/dec for L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> =55nm at room temperature are achieved with low voltages. The device also exhibits high ON-state current (~100μA/μm), as compared to other devices from this class. As a result, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> is realized with 0.5V gate swing for L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> =55nm MOSFETs. The excellent reliability is also demonstrated.