Micro Cu Bump Interconnection on 3D Chip Stacking Technology

Abstract

The three-dimensional (3D) chip stacking LSI technology under development at the Association of Super-Advanced Electronic Technologies (ASET) is a new packaging technology to realize high-density and high-speed transmission, and superfine flip-chip bonding technologies in 20-µm-pitch microbumps on Cu through-via (TV) are substantial technologies. As for advanced bonding technology, Cu bump bonding (CBB) utilizing Sn alloy is a simple process to connect Cu TVs directly without the formation of bumps on the device back surface, and the influence of the intermetallic compound (IMC) on the minute interconnection focusing on the bondability and reliability was verified, and the following results were obtained. The IMC state formed at the bonding interface depended on bonding temperature, and was confirmed as multilayered Cu 6 Sn 5 and Cu 3 Sn at 240°C, and single-layered Cu 3 Sn at 350°C. The IMC state is the governing factor of bondabilities of Cu bump interconnection in a 20-µm-pitch. The electroresistance value of the Cu bump interconnection was approximately 0.45 Ω, and no significant difference was confirmed under each condition. Young's modulus values of IMC (Cu 6 Sn 5 :112.6 GPa and Cu 3 Sn:132.7 GPa) were obtained by the nano-indentation test. The Sn-Ag layer as bonding material should be reduced to Cu-Sn IMC, and a low-rigid resin was preferable in terms of interconnection reliability based on the results of finite element method (FEM) analysis. Finally, the vertical interconnections utilizing CBB were formed, and the increase in electrical resistance by stacking one TV chip was approximately 0.03 Ω. Therefore, sufficient electrical vertical interconnection of Cu TV in a 20-µm-pitch was performed.