Record I<inf>ON</inf>/I<inf>OFF</inf> performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

Abstract

We report on a 65nm Ge pFET with a record performance of I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> = 478μA/μm and I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off,s</inf> = 37nA/μm @V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> = -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature Epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance.