Submicrometer InP/InGaAs DHBT Architecture Enhancements Targeting Reliability Improvements

Abstract

We report on the reliability of InP/InGaAs DHBTs used in very high speed ICs and present the analysis of HBT failure mechanisms after thermal and bias stresses (junction temperature from 87°C to 240°C, collector current density fixed at 400 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and collector-emitter voltage from 1.5 to 2.7 V). The physical origins of these failure mechanisms have been investigated using TCAD simulation. It points out the emitter sidewalls, the base-emitter junction periphery, and the emitter access resistance. Through three device generations, the analysis pointed out the successive technological enhancements to reduce the thermal resistance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> and subsequently decrease the self-heating, leading to minimizing the impact of failure mechanisms.