CONCAVE-DMOSFET: A New Super-Low On-Resistance Power MOSFET

Abstract

This paper describes a new super-low on-resistance power MOSFET. The new transistor “CONCAVE-DMOSFET” has a concave channel structure fabricated not by trench etching technique, but by a combination of local oxidation of silicon (LOCOS) and diffusion self-alignment using oxide film as a double diffusion mask. The CONCAVE-DMOSFET based on 16 µ m cell design has been fabricated for the first time, and the specific on-resistance of 75 mΩ· mm 2 with breakdown voltage of 50 V has been achieved. This specific on-resistance is the lowest ever reported for power MOSFETs of comparable same design rule. The lowest value has been realized by means of the CONCAVE-DMOS technology, which eliminates JFET resistance and provides a damage-free concave surface resulting in high channel mobility of 300 cm 2 /V·s.