Localized SOI technology: an innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications

Abstract

In this paper, we demonstrate the first successful integration of "localized SOI" devices integrated with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /TiN gate stack on dedicated areas of bulk CMOS substrates. We propose a low cost innovative approach based on the SON technology, where the buried sacrificial SiGe layer can be removed directly from the edges of the active area in a self-aligned process, to form an entire fully-depleted structure isolated from the substrate. NMOS devices with gate length down to 32 nm are demonstrated on 6 nm Si-films, allowing the control of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> current down to 0.1 nA/mum for 440 muA/mum I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> @Vdd=1.1 V. We also demonstrated the impact of the TiN (as metal gate) thickness and compressive CESL (contact etch stop layer) boosters for ultra-thin film PMOS, allowing +15% and +22% additional improvement in performances, respectively. This localized-SOI approach is dedicated to low power devices where the leakage reduction is crucial. The possibility for power management is also demonstrated thank to the very thin buried dielectric and to the ground-plane implantations, allowing body factor as high as 80 mV/Von short devices.