Improving the target impedance method for PCB decoupling of core power

Abstract

Decoupling core power for modern processors or SOCs is a challenging task due to large power consumption. The decoupling network designed by a commonly used target impedance approach is known to be very pessimistic and very difficult to implement. In this paper, a step surge current is identified as a major source of core power noise. By considering the ramp time of the surge current, we propose a modified target impedance method that significantly reduces the pessimism built into the original target impedance method. As an example, a real FPGA decoupling case is used to demonstrate the effectiveness of the new proposal.